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Technology, Applications, and Computation Ancient Roots Analog or Digital? Where Are We Now? Arithmetic and DSP Discrete Fourier Transform (DFT) Arithmetic Considerations Convolution Filtering with Exact Arithmetic The Double-Base Number System (DBNS) Motivation The Double-Base Number System The Greedy Algorithm Reduction Rules in the DBNS A Two-Dimensional Index Calculus Implementing DBNS Arithmetic Arithmetic Operations in the DBNS Conversion between Binary and DBNS Using Symbolic Substitution Analog Implementation Using Cellular Neural Networks Multiplier Design Based on DBNS Multiplication by a Constant Multiplier Using the DBNS DBNS Multiplication with Subquadratic Complexity General Multiplier Structure Results and Comparisons Some Multiplier Designs Example Applications The Multidimensional Logarithmic Number System (MDLNS) The Multidimensional Logarithmic Number System (MDLNS) Arithmetic Implementation in the MDLNS Multiple-Digit MDLNS Half-Domain MDLNS Filter Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Single-Digit 2DLNS Conversion Range-Addressable Lookup Table (RALUT) Two-Digit 2DLNS-to-Binary Conversion Binary-to-Two-Digit 2DLNS Conversion Multidigit 2DLNS Representation (n > 2) Extending to More Bases Physical Implementation Very Large-Bit Word Binary-to-DBNS Converter Multidimensional Logarithmic Number System: Addition and Subtraction MDLNS Representation Simple Single-Digit MDLNS Addition and Subtraction Classical Method Single-Base Domain Addition in the Single-Base Domain Subtraction in the Single-Base Domain Single-Digit MDLNS Addition/Subtraction Two-Digit MDLNS Addition/Subtraction MDLNS Addition/Subtraction with Quantization Error Recovery Comparison to an LNS Case Optimizing MDLNS Implementations Background Selecting an Optimal Base One-Bit Sign Architecture Example Finite Impulse Response Filter Extending the Optimal Base to Three Bases Integrated Circuit Implementations and RALUT Circuit Optimizations A 15th-Order Single-Digit Hybrid DBNS Finite Impulse Response (FIR) Filter A 53rd-Order Two-Digit DBNS FIR Filter A 73rd-Order Low-Power Two-Digit MDLNS Eight-Channel Filterbank Optimized 75th-Order Low-Power Two-Digit MDLNS Eight-Channel Filterbank A RISC-Based CPU with 2DLNS Signal Processing Extensions A Dynamic Address Decode Circuit for Implementing Range Addressable Look-Up Tables Exponentiation Using Binary-Fermat Number Representations Theoretical Background Finding Suitable Exponents Algorithm for Exponentiation with a Low Number of Regular Multiplications Complexity Analysis Using Exponential Diophantine Equations Experiments with Random Numbers A Comparison Analysis Final Comments