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Principles of Power Integrity for PDN Design--Simplified Vital Source e-bog
Larry D. Smith og Eric Bogatin
(2017)
Pearson International
399,00 kr.
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Principles of Power Integrity for PDN Design--Simplified Vital Source e-bog
Larry D. Smith og Eric Bogatin
(2017)
Pearson International
494,00 kr.
444,60 kr.
Leveres umiddelbart efter køb
Principles of Power Integrity for PDN Design--Simplified Vital Source e-bog
Larry D. Smith og Eric Bogatin
(2017)
Pearson International
581,00 kr.
522,90 kr.
Leveres umiddelbart efter køb
Principles of Power Integrity for PDN Design--Simplified
Robust and Cost Effective Design for High Speed Digital Products
Larry D. Smith og Eric Bogatin
(2017)
Sprog: Engelsk
Pearson Education, Limited
1.287,00 kr.
1.158,30 kr.
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Detaljer om varen
- 1. Udgave
- Vital Source 90 day rentals (dynamic pages)
- Udgiver: Pearson International (April 2017)
- Forfattere: Larry D. Smith og Eric Bogatin
- ISBN: 9780132735629R90
Consistently Design PDNs That Deliver Reliable Performance at the Right Cost Too often, PDN designs work inconsistently, and techniques that work in some scenarios seem to fail inexplicably in others. This book explains why and presents realistic processes for getting PDN designs right in any new product. Drawing on 60+ years of signal and power integrity experience, Larry Smith and Eric Bogatin show how to manage noise and electrical performance, and complement intuition with analysis to balance cost, performance, risk, and schedule. Throughout, they distill the essence of complex real-world problems, quantify core principles via approximation, and apply them to specific examples. For easy usage, dozens of key concepts and observations are highlighted as tips and listed in quick, chapter-ending summaries. Coverage includes • A practical, start-to-finish approach to consistently meeting PDN performance goals • Understanding how signals interact with interconnects • Identifying root causes of common problems, so you can avoid them • Leveraging analysis tools to efficiently explore design space and optimize tradeoffs • Analyzing impedance-related properties of series and parallel RLC circuits • Measuring low impedance for components and entire PDN ecologies • Predicting loop inductance from physical design features • Reducing peak impedances from combinations of capacitors • Understanding power and ground plane properties in the PDN interconnect • Taming signal integrity problems when signals change return planes • Reducing peak impedance created by on-die capacitance and package lead inductance • Controlling transient current waveform interactions with PDN features • Simple spreadsheet-based analysis techniques for quickly creating first-pass designs This guide will be indispensable for all engineers involved in PDN design, including product, board, and chip designers; system, hardware, component, and package engineers; power supply designers, SI and EMI engineers, sales engineers, and their managers.
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Detaljer om varen
- 1. Udgave
- Vital Source 180 day rentals (dynamic pages)
- Udgiver: Pearson International (April 2017)
- Forfattere: Larry D. Smith og Eric Bogatin
- ISBN: 9780132735629R180
Consistently Design PDNs That Deliver Reliable Performance at the Right Cost Too often, PDN designs work inconsistently, and techniques that work in some scenarios seem to fail inexplicably in others. This book explains why and presents realistic processes for getting PDN designs right in any new product. Drawing on 60+ years of signal and power integrity experience, Larry Smith and Eric Bogatin show how to manage noise and electrical performance, and complement intuition with analysis to balance cost, performance, risk, and schedule. Throughout, they distill the essence of complex real-world problems, quantify core principles via approximation, and apply them to specific examples. For easy usage, dozens of key concepts and observations are highlighted as tips and listed in quick, chapter-ending summaries. Coverage includes • A practical, start-to-finish approach to consistently meeting PDN performance goals • Understanding how signals interact with interconnects • Identifying root causes of common problems, so you can avoid them • Leveraging analysis tools to efficiently explore design space and optimize tradeoffs • Analyzing impedance-related properties of series and parallel RLC circuits • Measuring low impedance for components and entire PDN ecologies • Predicting loop inductance from physical design features • Reducing peak impedances from combinations of capacitors • Understanding power and ground plane properties in the PDN interconnect • Taming signal integrity problems when signals change return planes • Reducing peak impedance created by on-die capacitance and package lead inductance • Controlling transient current waveform interactions with PDN features • Simple spreadsheet-based analysis techniques for quickly creating first-pass designs This guide will be indispensable for all engineers involved in PDN design, including product, board, and chip designers; system, hardware, component, and package engineers; power supply designers, SI and EMI engineers, sales engineers, and their managers.
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Detaljer om varen
- 1. Udgave
- Vital Source 365 day rentals (dynamic pages)
- Udgiver: Pearson International (April 2017)
- Forfattere: Larry D. Smith og Eric Bogatin
- ISBN: 9780132735629R365
Consistently Design PDNs That Deliver Reliable Performance at the Right Cost Too often, PDN designs work inconsistently, and techniques that work in some scenarios seem to fail inexplicably in others. This book explains why and presents realistic processes for getting PDN designs right in any new product. Drawing on 60+ years of signal and power integrity experience, Larry Smith and Eric Bogatin show how to manage noise and electrical performance, and complement intuition with analysis to balance cost, performance, risk, and schedule. Throughout, they distill the essence of complex real-world problems, quantify core principles via approximation, and apply them to specific examples. For easy usage, dozens of key concepts and observations are highlighted as tips and listed in quick, chapter-ending summaries. Coverage includes • A practical, start-to-finish approach to consistently meeting PDN performance goals • Understanding how signals interact with interconnects • Identifying root causes of common problems, so you can avoid them • Leveraging analysis tools to efficiently explore design space and optimize tradeoffs • Analyzing impedance-related properties of series and parallel RLC circuits • Measuring low impedance for components and entire PDN ecologies • Predicting loop inductance from physical design features • Reducing peak impedances from combinations of capacitors • Understanding power and ground plane properties in the PDN interconnect • Taming signal integrity problems when signals change return planes • Reducing peak impedance created by on-die capacitance and package lead inductance • Controlling transient current waveform interactions with PDN features • Simple spreadsheet-based analysis techniques for quickly creating first-pass designs This guide will be indispensable for all engineers involved in PDN design, including product, board, and chip designers; system, hardware, component, and package engineers; power supply designers, SI and EMI engineers, sales engineers, and their managers.
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Detaljer om varen
- Hardback: 816 sider
- Udgiver: Pearson Education, Limited (Marts 2017)
- Forfattere: Larry D. Smith og Eric Bogatin
- ISBN: 9780132735551
This guide's authors are the industry's leading experts in signal integrity and PDN. Smith has over 30 years' experience in electronics, system and PDN design at IBM, Sun Microsystems and Altera Corporation, and has architected today's most popular systematic approach to PDN design. Bogatin also has more than 30 years' experience in signal integrity, and has written the field's most popular SI text book, Signal and Power Integrity-Simplified.
Here, they thoroughly illuminate the core principles at the foundation of PDN performance, including impedance, resonance, inductance, and signal propagation. They offer practical insights for understanding noise sources, and show how design features affect noise. Next, they help readers strengthen their intuition about how physical design decisions affect electrical performance, and complement their intuition with detailed analysis to carefully balance cost and robustness.
Readers will find valuable rules of thumb, analytical approximations, examples of numerical simulations, and practical coverage of all PDN elements, from chip features to package, board, and voltage regulator module (VRM). The authors show to use measurement to anchor your designs to reality, characterizing components in the frequency domain, and characterizing systems in the time domain. They review the principles behind each measurement technique, as present multiple examples of measured performance of real world components and systems.
Preface xix Acknowledgments xxvii About the Authors xxix
Chapter 1 Engineering the Power Delivery Network 1
1.1 What Is the Power Delivery Network (PDN) and Why Should I Care? 1
1.2 Engineering the PDN 5
1.3 "Working" or "Robust" PDN Design 8
1.4 Sculpting the PDN Impedance Profile 12
1.5 The Bottom Line 14 Reference 15
Chapter 2 Essential Principles of Impedance for PDN Design 17
2.1 Why Do We Care About Impedance? 17
2.2 Impedance in the Frequency Domain 18
2.3 Calculating or Simulating Impedance 21
2.4 Real Circuit Components vs Ideal Circuit Elements 26
2.5 The Series RLC Circuit 30
2.6 The Parallel RLC Circuit 34
2.7 The Resonant Properties of a Series and Parallel RLC Circuit 36
2.8 Examples of RLC Circuits and Real Capacitors 42
2.9 The PDN as Viewed by the Chip or by the Board 46
2.10 Transient Response 52
2.11 Advanced Topic: The Impedance Matrix 56
2.12 The Bottom Line 66 References 68
Chapter 3 Measuring Low Impedance 69
3.1 Why Do We Care About Measuring Low Impedance? 69
3.2 Measurements Based on the V/I Definition of Impedance 70
3.3 Measuring Impedance Based on the Reflection of Signals 71
3.4 Measuring Impedance with a VNA 76
3.5 Example: Measuring the Impedance of Two Leads in a DIP 81
3.6 Example: Measuring the Impedance of a Small Wire Loop 86
3.7 Limitations of VNA Impedance Measurements at Low Frequency 89
3.8 The Four-Point Kelvin Resistance Measurement Technique 93
3.9 The Two-Port Low Impedance Measurement Technique 95
3.10 Example: Measuring the Impedance of a 1-inch Diameter Copper Loop 102
3.11 Accounting for Fixture Artifacts 105
3.12 Example: Measured Inductance of a Via 109
3.13 Example: Small MLCC Capacitor on a Board 114
3.14 Advanced Topic: Measuring On-Die Capacitance 120
3.15 The Bottom Line 134 References 136
Chapter 4 Inductance and PDN Design 137
4.1 Why Do We Care About Inductance in PDN Design? 137
4.2 A Brief Review of Capacitance to Put Inductance in Perspective 138
4.3 What Is Inductance? Essential Principles of Magnetic Fields and Inductance 141
4.4 Impedance of an Inductor 147
4.5 The Quasi-Static Approximation for Inductance 150
4.6 Magnetic Field Density, B 155
4.7 Inductance and Energy in the Magnetic Field 159
4.8 Maxwell''s Equations and Loop Inductance 163
4.9 Internal and External Inductance and Skin Depth 167
4.10 Loop and Partial, Self- and Mutual Inductance 172
4.11 Uniform Round Conductors 175
4.12 Approximations for the Loop Inductance of Round Loops 179
4.13 Loop Inductance of Wide Conductors Close Together 182
4.14 Approximations for the Loop Inductance of Any Uniform Transmission Line 188
4.15 A Simple Rule of Thumb for Loop Inductance 194
4.16 Advanced Topic: Extracting Loop Inductance from the S-parameters Calculated with a 3D Field Solver 195
4.17 The Bottom Line 202 References 204
Chapter 5 Practical Multi-Layer Ceramic Chip Capacitor Integration 205
5.1 Why Use Capacitors? 205
5.2 Equivalent Circuit Models for Real Capacitors 206
5.3 Combining Multiple Identical Capacitors in Parallel 209
5.4 The Parallel Resonance Frequency Between Two Different Capacitors 211
5.5 The Peak Impedance at the PRF 215
5.6 Engineering the Capacitance of a Capacitor 220
5.7 Capacitor Temperature and Voltage Stability 222
5.8 How Much Capacitance Is Enough? 225
5.9 The ESR of Real Capacitors: First- and Second-Order Models 229
5.10 Estimating the ESR of Capacitors from Spec Sheets 234
5.11 Controlled ESR Capacitors 238
5.12 Mounting Inductance of a Capacitor 240
5.13 Using Vendor-Supplied S-parameter Capacitor Models 251
5.14 How to Analyze Vendor-Supplied S-Parameter Models 254
5.15 Advanced Topics: A Higher Bandwidth Capacitor Model 258
5.16 The Bottom Line 272 References 274
Chapter 6 Properties of Planes and Capacitors 275
6.1 The Key Role of Planes 275
6.2 Low-Frequency Property of Planes: Parallel Plate Capacitance 278
6.3 Low-Frequency Property of Planes: Fringe Field Capacitance 279
6.4 Low-Frequency Property of Planes: Fringe Field Capacitance in Power Puddles 285
6.5 Loop Inductance of Long, Narrow Cavities 290
6.6 Spreading Inductance in Wide Cavities 292
6.7 Extracting Spreading Inductance from a 3D Field Solver 304
6.8 Lumped-Circuit Series and Parallel Self-Resonant Frequency 307
6.9 Exploring the Features of the Series LC Resonance 312
6.10 Spreading Inductance and Source Contact Location 315
6.11 Spreading Inductance Between Two Contact Points 317
6.12 The Interactions of a Capacitor and Cavities 325
6.13 The Role of Spreading Inductance: When Does Capacitor Location Matter? 327
6.14 Saturating the Spreading Inductance 332
6.15 Cavity Modal Resonances and Transmission Line Properties 334
6.16 Input Impedance of a Transmission Line and Modal Resonances 340
6.17 Modal Resonances and Attenuation 343
6.18 Cavity Modes in Two Dimensions 347
6.19 Advanced Topic: Using Transfer Impedance to Probe Spreading Inductance 354
6.20 The Bottom Line 361 References 362
Chapter 7 Taming Signal Integrity Problems When Signals Change Return Planes 363
7.1 Signal Integrity and Planes 363
7.2 Why the Peak Impedances Matter 364
7.3 Reducing Cavity Noise through Lower Impedance and Higher Damping 367
7.4 Suppressing Cavity Resonances with Shorting Vias 372
7.5 Suppressing Cavity Resonances with Many DC Blocking Capacitors 383
7.6 Estimating the Number of DC Blocking Capacitors to Suppress Cavity Resonances 387
7.7 Determining How Many DC Blocking Capacitors Are Needed to Carry Return Current 393
7.8 Cavity Impedance with a Suboptimal Number of DC Blocking Capacitors 397
7.9 Spreading Inductance and Capacitor Mounting Inductance 401
7.10 Using Damping to Suppress Parallel Resonant Peaks Created by a Few Capacitors 403
7.11 Cavity Losses and Impedance Peak Reduction 408
7.12 Using Multiple Capacitor Values to Suppress Impedance Peak 411
7.13 Using Controlled ESR Capacitors to Reduce Peak Impedance Heights 414
7.14 Summary of the Most Important Design
Chapter 1 Engineering the Power Delivery Network 1
1.1 What Is the Power Delivery Network (PDN) and Why Should I Care? 1
1.2 Engineering the PDN 5
1.3 "Working" or "Robust" PDN Design 8
1.4 Sculpting the PDN Impedance Profile 12
1.5 The Bottom Line 14 Reference 15
Chapter 2 Essential Principles of Impedance for PDN Design 17
2.1 Why Do We Care About Impedance? 17
2.2 Impedance in the Frequency Domain 18
2.3 Calculating or Simulating Impedance 21
2.4 Real Circuit Components vs Ideal Circuit Elements 26
2.5 The Series RLC Circuit 30
2.6 The Parallel RLC Circuit 34
2.7 The Resonant Properties of a Series and Parallel RLC Circuit 36
2.8 Examples of RLC Circuits and Real Capacitors 42
2.9 The PDN as Viewed by the Chip or by the Board 46
2.10 Transient Response 52
2.11 Advanced Topic: The Impedance Matrix 56
2.12 The Bottom Line 66 References 68
Chapter 3 Measuring Low Impedance 69
3.1 Why Do We Care About Measuring Low Impedance? 69
3.2 Measurements Based on the V/I Definition of Impedance 70
3.3 Measuring Impedance Based on the Reflection of Signals 71
3.4 Measuring Impedance with a VNA 76
3.5 Example: Measuring the Impedance of Two Leads in a DIP 81
3.6 Example: Measuring the Impedance of a Small Wire Loop 86
3.7 Limitations of VNA Impedance Measurements at Low Frequency 89
3.8 The Four-Point Kelvin Resistance Measurement Technique 93
3.9 The Two-Port Low Impedance Measurement Technique 95
3.10 Example: Measuring the Impedance of a 1-inch Diameter Copper Loop 102
3.11 Accounting for Fixture Artifacts 105
3.12 Example: Measured Inductance of a Via 109
3.13 Example: Small MLCC Capacitor on a Board 114
3.14 Advanced Topic: Measuring On-Die Capacitance 120
3.15 The Bottom Line 134 References 136
Chapter 4 Inductance and PDN Design 137
4.1 Why Do We Care About Inductance in PDN Design? 137
4.2 A Brief Review of Capacitance to Put Inductance in Perspective 138
4.3 What Is Inductance? Essential Principles of Magnetic Fields and Inductance 141
4.4 Impedance of an Inductor 147
4.5 The Quasi-Static Approximation for Inductance 150
4.6 Magnetic Field Density, B 155
4.7 Inductance and Energy in the Magnetic Field 159
4.8 Maxwell''s Equations and Loop Inductance 163
4.9 Internal and External Inductance and Skin Depth 167
4.10 Loop and Partial, Self- and Mutual Inductance 172
4.11 Uniform Round Conductors 175
4.12 Approximations for the Loop Inductance of Round Loops 179
4.13 Loop Inductance of Wide Conductors Close Together 182
4.14 Approximations for the Loop Inductance of Any Uniform Transmission Line 188
4.15 A Simple Rule of Thumb for Loop Inductance 194
4.16 Advanced Topic: Extracting Loop Inductance from the S-parameters Calculated with a 3D Field Solver 195
4.17 The Bottom Line 202 References 204
Chapter 5 Practical Multi-Layer Ceramic Chip Capacitor Integration 205
5.1 Why Use Capacitors? 205
5.2 Equivalent Circuit Models for Real Capacitors 206
5.3 Combining Multiple Identical Capacitors in Parallel 209
5.4 The Parallel Resonance Frequency Between Two Different Capacitors 211
5.5 The Peak Impedance at the PRF 215
5.6 Engineering the Capacitance of a Capacitor 220
5.7 Capacitor Temperature and Voltage Stability 222
5.8 How Much Capacitance Is Enough? 225
5.9 The ESR of Real Capacitors: First- and Second-Order Models 229
5.10 Estimating the ESR of Capacitors from Spec Sheets 234
5.11 Controlled ESR Capacitors 238
5.12 Mounting Inductance of a Capacitor 240
5.13 Using Vendor-Supplied S-parameter Capacitor Models 251
5.14 How to Analyze Vendor-Supplied S-Parameter Models 254
5.15 Advanced Topics: A Higher Bandwidth Capacitor Model 258
5.16 The Bottom Line 272 References 274
Chapter 6 Properties of Planes and Capacitors 275
6.1 The Key Role of Planes 275
6.2 Low-Frequency Property of Planes: Parallel Plate Capacitance 278
6.3 Low-Frequency Property of Planes: Fringe Field Capacitance 279
6.4 Low-Frequency Property of Planes: Fringe Field Capacitance in Power Puddles 285
6.5 Loop Inductance of Long, Narrow Cavities 290
6.6 Spreading Inductance in Wide Cavities 292
6.7 Extracting Spreading Inductance from a 3D Field Solver 304
6.8 Lumped-Circuit Series and Parallel Self-Resonant Frequency 307
6.9 Exploring the Features of the Series LC Resonance 312
6.10 Spreading Inductance and Source Contact Location 315
6.11 Spreading Inductance Between Two Contact Points 317
6.12 The Interactions of a Capacitor and Cavities 325
6.13 The Role of Spreading Inductance: When Does Capacitor Location Matter? 327
6.14 Saturating the Spreading Inductance 332
6.15 Cavity Modal Resonances and Transmission Line Properties 334
6.16 Input Impedance of a Transmission Line and Modal Resonances 340
6.17 Modal Resonances and Attenuation 343
6.18 Cavity Modes in Two Dimensions 347
6.19 Advanced Topic: Using Transfer Impedance to Probe Spreading Inductance 354
6.20 The Bottom Line 361 References 362
Chapter 7 Taming Signal Integrity Problems When Signals Change Return Planes 363
7.1 Signal Integrity and Planes 363
7.2 Why the Peak Impedances Matter 364
7.3 Reducing Cavity Noise through Lower Impedance and Higher Damping 367
7.4 Suppressing Cavity Resonances with Shorting Vias 372
7.5 Suppressing Cavity Resonances with Many DC Blocking Capacitors 383
7.6 Estimating the Number of DC Blocking Capacitors to Suppress Cavity Resonances 387
7.7 Determining How Many DC Blocking Capacitors Are Needed to Carry Return Current 393
7.8 Cavity Impedance with a Suboptimal Number of DC Blocking Capacitors 397
7.9 Spreading Inductance and Capacitor Mounting Inductance 401
7.10 Using Damping to Suppress Parallel Resonant Peaks Created by a Few Capacitors 403
7.11 Cavity Losses and Impedance Peak Reduction 408
7.12 Using Multiple Capacitor Values to Suppress Impedance Peak 411
7.13 Using Controlled ESR Capacitors to Reduce Peak Impedance Heights 414
7.14 Summary of the Most Important Design
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